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HFA1103
Data Sheet March 1999 File Number 3957.3
200MHz, Video Op Amp with High Speed Sync Stripper
The HFA1103 is a high-speed, wideband, fast settling current feedback op amp with a sync stripping function. The HFA1103 is a basic op amp with a modified output stage that enables it to strip the sync from a component video signal. The output stage has an open emitter NPN transistor that prevents the output from going low during the sync pulse. Removing the sync signal benefits digitizing systems because only the active video information is applied to the A/D converter. This enables the full dynamic range of the A/D converter to be used to process the video signal. The HFA1103 includes inverting input bias current adjust pins (pins 1 and 5) for adjusting the output offset voltage.
Features
* Removes Sync Signal From Component Video * Low Residual Sync . . . . . . . . . . . . . . . . . . . . . . 8mV (Typ) * -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 200MHz * Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 600V/s * Fast Settling Time (0.1%) . . . . . . . . . . . . . . . . . . . . . . 9ns * Excellent Gain Flatness, 32MHz . . . . . . . . . . . . . . 0.1dB * Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . <12ns
Applications
* RGB Video Sync Stripping * RGB Video Distribution Amplifier for Workstations and PC Networks
Ordering Information
PART NUMBER (BRAND) HFA1103IB (H1103I) TEMP. RANGE (oC) -40 to 85 PACKAGE 8 Ld SOIC PKG. NO. M8.15
* Video Conferencing Systems * RGB Video Monitor Preamp * Fiberoptic Receivers
Sync Stripper Waveforms
0 TO +0.7V 0 TO -0.3V COMPONENT (RGB) VIDEO INPUT HFA1103 OUTPUT 0 TO +0.7V
Pinout
HFA1103 (SOIC) TOP VIEW
BAL -IN +IN V-
1 2 3 4 V+
8 7 6 5
NC V+ OUT BAL
+
Application Schematic
+5V 4.7K RB HFA1103 VIN RIN 75 RG 750 + 2K VOUT RT 75 RL 75 RT 75
-
RF 750
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HFA1103
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DC CHARACTERISTICS Residual Sync (Note 2)
VSUPPLY = 5V, AV = +2, RF = 750, RL = 50, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS
VIN = -300mV, AV = +1
25 Full
39 35 100 25 2.5 -
8 10 10 45 5 5 200 50 16 2 3.0 4 18 21
10 12 30 40 40 65 50 60 30 -
mV mV mV mV V/oC dB dB A A A A A k pF V nV/Hz pA/Hz pA/Hz
Output Offset Voltage (Notes 3, 5)
25 Full
Output Offset Voltage Drift (Note 3) VOS PSRR Non-Inverting Input Bias Current VS = 1.25V +IN = 0V
Full 25 Full 25 Full
Inverting Input Bias Current
-IN = 0V
25 Full
-IBIAS Adjust Range (Notes 4, 6) Non-Inverting Input Resistance Inverting Input Resistance Input Capacitance Input Common Mode Range Input Noise Voltage +Input Noise Current -Input Noise Current 100kHz 100kHz 100kHz
25 25 25 25 Full 25 25 25
TRANSFER CHARACTERISTICS AV = +2, Unless Otherwise Specified Open Loop Transimpedance -3dB Bandwidth Gain Flatness Minimum Stable Gain OUTPUT CHARACTERISTICS AV = +2, Unless Otherwise Specified Output Voltage (Note 3) 25, 85 -40oC Output Current 25, 85 -40oC Linearity Near Zero TRANSIENT RESPONSE Rise Time AV = +2, Unless Otherwise Specified VOUT = 2.0V Step 25 2 ns 25 2.5 1.75 50 35 3.0 2.5 60 50 0.01 V V mA mA % VOUT = 1.0VP-P, AV = +2 To 0.1dB 25 25 25 Full 1 500 200 32 k MHz MHz V/V
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HFA1103
Electrical Specifications
PARAMETER Overshoot Slew Rate 0.1% Settling Overdrive Recovery Time POWER SUPPLY CHARACTERISTICS Supply Voltage Range Supply Current (No Load) Full 25 Full NOTES: 2. The residual sync is specified at the output of a doubly terminated circuit (see page 1 of this data sheet). 3. Since the HFA1103 has an open emitter NPN output stage, this measurement is only valid for positive values. 4. The -IBIAS current can be used to adjust the offset voltage to zero, but -IBIAS does not flow bidirectionally because the HFA1103 output stage is an open emitter NPN transistor. 5. VOS includes the error contribution of IBSN at RF = 750. 6. This is the minimum change in inverting input bias current when a BAL pin is connected to V- through a 50 resistor. 4.5 11 5.5 16 23 V mA mA VSUPPLY = 5V, AV = +2, RF = 750, RL = 50, Unless Otherwise Specified (Continued) TEST CONDITIONS VOUT = 2.0V Step AV = +2, VOUT = 0 to 2V, +2V to 0V VOUT = 2V to 0V 2X Overdrive TEMP (oC) 25 25 25 25 MIN TYP 10 600 9 12 MAX UNITS % V/s ns ns
Test Circuit
DUT VIN +
may cause oscillations. In most cases, the oscillation can be avoided by placing a resistor in series with the output.
VOUT
-
RIN 50
RG 750
RF 750
RL 50
FIGURE 1. TEST CIRCUIT
Care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 3.
Application Information
Offset Adjustment
The HFA1103 allows for adjustment of the inverting input bias current to null the output offset voltage. -IBIAS flows through RF, so any change in bias current forces a corresponding change in output voltage. The amount of adjustment is a function of RF. With RF = 750, the typical adjust range is 150mV. For offset adjustment connect a 10k potentiometer between pins 1 and 5 with the wiper connected to V-.
Evaluation Board
The HFA1100 series evaluation board may be used for the HFA1103 with minor modifications. The evaluation board may be ordered using part number HFA11XXEVAL. Please note that an HFA1103 sample is not included with the evaluation board and must be ordered separately. The layout and schematic of the board are shown below:
500 1 50 IN 2 3 4 10F 0.1F -5V GND 500 VH 8 7 50 6 5 GND OUT VL 0.1F 10F +5V
PC Board Layout
The frequency performance of these amplifiers depends a great deal on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value chip (0.1F) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and 3
FIGURE 2. EVALUATION BOARD SCHEMATIC
HFA1103
TOP LAYOUT
VH 1 +IN VL VV+ GND OUT
BOTTOM LAYOUT
Typical Application
A circuit which performs the sync stripper and DC restore functions is shown in Figure 4. Please reference Intersil Application Note AN9514, titled "Video Amplifier with Sync Stripper and DC Restore", for details on this circuit.
FIGURE 3. EVALUATION BOARD ARTWORK
The standard output of a VM700 video measurement set is shown in Figure 5. The output, after passing through the Applications Schematic shown on the first page of this data sheet, is shown in Figure 6.
TO SYNC SEPARATOR S/H CONTROL IC1a + R1 1K VIN OPT. R2 10K IC2 C1 0.1F
+5V R3 10K -5V + IC1b R6 750
IC1a + IC1b = CA5260 DUAL AMP IC2 = 74HC4053 SWITCH IC3 = HFA1103 VIDEO OP AMP R7 750 R8 6.8K +5VDC IC3 R11 75 VOUT R10 75 R9 10K R12 75
-
-
+ C2 47F
R4 1K
R5 1K
FIGURE 4. VIDEO AMPLIFIER WITH SYNC STRIPPER AND DC RESTORE
VOLTS IRE:FLT 100.0 0.6
0.4 50.0
0.2
0.0
0.0
-0.2 -50.0 -40.0 525 LINE NTSC -30.0 -20.0 -10.0 0.0 10.0
MICROSECONDS
FIGURE 5. OUTPUT OF VM700 VIDEO MEASUREMENT SET
4
HFA1103
VOLTS
IRE:FLT 100.0
0.6
0.4 50.0
0.2
0.0
0.0
-0.2
-50.0 -40.0 525 LINE NTSC -30.0 -20.0 -10.0 0.0 10.0
MICROSECONDS
FIGURE 6. OUTPUT OF HFA1103 SYNC STRIPPER CONFIGURED AS ON THE FIRST PAGE OF THIS DATA SHEET
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HFA1103 Die Characteristics
DIE DIMENSIONS: 63 mils x 44 mils x 19 mils 1600m x 1130m x 483m METALLIZATION: Type: Metal 1: AlCu (2%)/TiW Thickness: Metal1: 8kA 0.4kA Type: Metal 2: AlCu (2%) Thickness: 16kA 0.8kA SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-) PASSIVATION: Type: Nitride Thickness: 4kA 0.5kA TRANSISTOR COUNT: 50
Metallization Mask Layout
HFA1103
BAL NC
-IN
V+
+IN
OUT
V-
NC
BAL
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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HFA1103 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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